[COMGR][HotSwap] Fix M32 scaled WMMA lowering

[paulzzy]

Jira: ROCM-28594

Summary

Fix regular-scale and Scale16 M32 WMMA lowering for gfx1250 B0-to-A0
HotSwap.

The change:

• splits regular-scale M32 operations into two exact M16 operations and uses
  MATRIX_SCALE_ROW1 for the upper M half;
• replaces in-place Scale16 A/scale mutation with generated bank-zero scratch;
• executes M0 low/high followed by M1 low/high;
• keeps masked A contiguous while allowing four generated scales and the
  gather temporary to use independent dead low-bank VGPRs;
• avoids unnecessary VGPR growth when 13 dead registers are available but are
  not one contiguous interval;
• consumes legacy gfx1250 tensor instructions through canonical LLVM MC
  decoding instead of COMGR raw-byte classifiers;
• exposes stable AMDGPU named operand roles to MC clients and builds the WMMA
  replacement instructions from structured MCOperands rather than parsing
  MCInstPrinter text or mirroring positional operand layouts;
• reuses a locally dead, already-declared SGPR for saturated required tensor
  wrappers when current-text CFG liveness proves it safe;
• rechecks only required tensor trampolines after final pool layout and
  promotes a shifted out-of-range short return into the transactional
  branch-island path merged in PR [comgr][hotswap] Make branch-island allocation transactional ROCm/llvm-project#3677.

Review scope

The PR base branch mirrors ROCm/llvm-project:amd-staging at
7f7448fc5af9.

Please review these 11 signed commits in order:

1. 63c2b1e1136e - decode the observed legacy gfx1250 tensor DMA aliases as
   canonical LLVM MC instructions;
2. c72aecf655ac - exact M32 Scale16 lowering;
3. 83608054a2b2 - make the M32 Scale16 lowering bank-safe;
4. 892dafb85d8d - drain XCNT across M32 VGPR bank changes;
5. bd3c63223442 - fix regular/Scale16 M32 splitting, preserve original
   operands, and support fragmented scratch;
6. 452bd2650f3e - remove temporary raw tensor classifiers and consume LLVM
   MC semantics;
7. 4f76e8635f84 - add legacy tensor integration coverage;
8. d1dec3d5f3ff - route required tensor wrappers in saturated kernels;
9. 09e071d5e59e - expose a public AMDGPU named-operand adapter;
10. c2932c4e05d8 - add shared COMGR named-MC helpers;
11. f456866e0d33 - remove printer parsing and build WMMA splits from
    structured operands.

Commits 2-4 preserve @harsh-amd's original implementation history. The primary
corrective review is commits 5-11.

Root cause

ROCM-28594 tracks 416 parameterized Triton/Gluon
test_amd_wmma_scaled failures. The failing kernels use the B0-only
32x16x128 FP4 WMMA shape:

• 208 cases use E8M0 scale encoding;
• 208 cases use E4M3 scale encoding;
• both groups exercise MXFP4 matrix operands.

A representative reproducer is a non-transposed M=32, N=32, K=128
FP4-by-FP4 kernel with both E8M0 scales enabled. It emits
v_wmma_scale_f32_32x16x128_f4 as intended on B0, but the HotSwapped result
is numerically incorrect on A0.

A0 does not provide the M32 instruction directly. Regular scaled WMMA must be
split into two M16 operations. Scale16 M32 additionally needs a K-subblock
split, producing four exact M16 block-32 WMMAs.

The earlier Scale16 lowering modified matrix A and both scale pairs in place.
That corrupts kernels where only one matrix operand is scaled because later
generated passes still need the original A and scale values. Fully scaled
variants can fail for the same reason when the generated M/K passes reuse
mutated inputs.

Larger parameter combinations also expose a scratch-allocation failure. A
representative 128-VGPR kernel has an eight-register dead low-bank interval
plus five independently dead low-bank registers, but no contiguous
13-register interval. Requiring all scratch to be contiguous grows the kernel
by 13 VGPRs. That changes the metadata note size, prevents a size-preserving
rewrite, and leaves the original B0-only instruction for A0 execution.

The final allocation keeps only the eight masked-A registers contiguous and
allocates the four generated scales and temporary independently. Original A
and scale operands are never modified.

The prior implementation also reconstructed WMMA replacements from printed
assembly text and duplicated backend operand positions. That was fragile for
inline floating-point immediates, modifiers, tied operands, and aliased
source/destination operands. The final implementation queries named operand
roles, transforms MCInsts directly, copies the original MCOperand values,
and emits the result through MCCodeEmitter.

Canonical decoding also exposes required legacy tensor wrappers in kernels
whose declared SGPR footprint is saturated. Those kernels can still have a
register that is dead across the wrapper and its continuation. The fallback
uses current-text CFG liveness to reuse that register without metadata growth.
If final trampoline layout shifts a required short return out of range, the
site is promoted into PR ROCm#3677's transactional registerless island path.

Testing

LLVM MC:

• legacy and canonical gfx1250 tensor MC tests pass;
• the exact 12-byte legacy record decodes as canonical
  TENSOR_LOAD_TO_LDS_d4_gfx1250.

Host Release:

• HotswapMCTests: 194/194;
• focused WMMA LIT: 41/41;
• full supported COMGR LIT: 166/166;
• CTest: 32/32.

Clang-19 ASan:

• focused HotswapMCTests: 194/194;
• focused WMMA LIT: 41/41;
• full supported COMGR LIT: 166/166.

A0 numerical validation:

• one-sided Scale16 regression: 1/1 passed with candidate-load proof;
• complete M32 wmma_shape1 family: 208 passed, 3,536 skipped, zero failed;
• pre/post device-holder audits were clean.

The numerical runs preserved 169 unique Triton input HSACOs. Rewriting all
169 with the prior numerically validated candidate and this candidate produced
169/169 byte-identical, idempotent outputs with zero status or hash changes.

20,442-object corpus:

• parent: 20,382 pass / 58 fail / 2 established timeout;
• candidate: 20,392 pass / 48 fail / 2 established timeout;
• status changes: ten previously failing inputs -> pass, zero pass -> fail;
• common outputs: 20,381 unchanged, one expected Scale16 output changed;
• candidate-only outputs: ten;
• all 20,392 emitted outputs passed ELF validation and byte-identical second
  rewrite.

The full host and A0 validation above was completed on the merged-ROCm#3677
amd-staging tip used during development. The final refresh onto live
amd-staging (7f7448fc5af9) was conflict-free; all 11 stable patch IDs and
the complete git range-diff are identical, and git diff --check passes.