FROMLIST: arm64: dts: qcom: glymur: Enable LLCC/DDR/DDR_QOS DVFS#1471
FROMLIST: arm64: dts: qcom: glymur: Enable LLCC/DDR/DDR_QOS DVFS#1471Pragnesh Papaniya (ppapaniy) wants to merge 1 commit into
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On Qualcomm Glymur SoCs, the memlat governor and the mechanism for controlling the LLCC and DDR/DDR_QOS frequencies run on the CPU Control Processor (CPUCP). Add the CPUCP mailbox and SCMI nodes required for the QCOM SCMI Generic Extension protocol to probe and get functional bus dvfs on Glymur/Mahua SoCs. Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com> Signed-off-by: Pragnesh Papaniya <pragnesh.papaniya@oss.qualcomm.com> Link: https://lore.kernel.org/lkml/20260610-rfc_v7_scmi_memlat-v7-8-f3f68c608f25@oss.qualcomm.com/
🔨 Build Failure Analysis — PR #1471PR: #1471
VerdictThis is not a compilation error. The build failed during the integration merge phase when attempting to merge PR #1471 into topic branch 📎 Detailed analysis: Full report |
🔨 Build Failure Analysis — PR #1471PR: #1471
VerdictThis is not a compilation failure. The build failed during the automerge/integration phase with 101 merge conflicts. Only 1 conflict ( 📎 Detailed analysis: Full report |
PR #1471 — validate-patchPR: #1471
Final Summary
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PR #1471 — checker-log-analyzerPR: #1471
Detailed report: Full report
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On Qualcomm Glymur SoCs, the memlat governor and the mechanism for controlling the LLCC and DDR/DDR_QOS frequencies run on the CPU Control Processor (CPUCP). Add the CPUCP mailbox and SCMI nodes required for the QCOM SCMI Generic Extension protocol to probe and get functional bus dvfs on Glymur/Mahua SoCs.
Link: https://lore.kernel.org/lkml/20260610-rfc_v7_scmi_memlat-v7-8-f3f68c608f25@oss.qualcomm.com/