MIPS

A very work-intensive project that implemented a 5-stage MIPS ISA pipeline CPU on Xilinx SP6 FPGA kit. Using VHDL.

Name		Name	Last commit message	Last commit date
iseconfig		iseconfig
pipeline files		pipeline files
testbench		testbench
uart		uart
Debugging Part.docx		Debugging Part.docx
DualPortMem.vhd		DualPortMem.vhd
HostComm.vhd		HostComm.vhd
LICENSE		LICENSE
MIPSProcessor_with_PC_inside.vhd		MIPSProcessor_with_PC_inside.vhd
MIPSSystem.vhd		MIPSSystem.vhd
MIPS_ALU.vhd		MIPS_ALU.vhd
MIPS_ALU_ctrl.vhd		MIPS_ALU_ctrl.vhd
MIPS_PC_with_src_select.vhd		MIPS_PC_with_src_select.vhd
MIPS_main_controller_sincle_cycle_redesign.vhd		MIPS_main_controller_sincle_cycle_redesign.vhd
MIPS_sign_extender_and_shifter.vhd		MIPS_sign_extender_and_shifter.vhd
README.md		README.md
cpu_controller.vhd		cpu_controller.vhd
datapath.vhd		datapath.vhd
reg_file.vhd		reg_file.vhd

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