GitHub - vidushv/SIMD-Image-Processor

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db		db
incremental_db		incremental_db
matlab		matlab
output_files		output_files
picsAndCode		picsAndCode
rtl		rtl
simulation/modelsim		simulation/modelsim
tb		tb
work		work
DE2_pin_assignments.csv		DE2_pin_assignments.csv
Data_Distributer.v		Data_Distributer.v
README		README
lab6.out.sdc		lab6.out.sdc
lab6.pdf		lab6.pdf
lab6.qpf		lab6.qpf
lab6.qsf		lab6.qsf
lab6.qsf.bak		lab6.qsf.bak
lab6.qws		lab6.qws
lab6.sdc		lab6.sdc
ram.v		ram.v
ram.v.bak		ram.v.bak
sim.cr.mti		sim.cr.mti
sim.mpf		sim.mpf
tb_lab6.v		tb_lab6.v
tb_lab6.v.bak		tb_lab6.v.bak
top.v		top.v
top.v.bak		top.v.bak
vsim.wlf		vsim.wlf
wlft8zemjm		wlft8zemjm

Repository files navigation

Provided files for EEC180B Lab exercist.

Lab6.pdf - Document with the lab description
rtl      - UART transmitter and receiver verilog
tb       - Testbench aid for design work
matlab   - MATLAB scripts and images sets.