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Fixing Access to the Main Memory by Cache/UART in Simulation - #132

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Joao-Pedro-Cabral:cache_uart
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Fixing Access to the Main Memory by Cache/UART in Simulation#132
Joao-Pedro-Cabral wants to merge 2 commits into
vproc:mainfrom
Joao-Pedro-Cabral:cache_uart

Fixing trace if bound

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