perf(gfx1201): enable AlpineQ R4/R8 Q8 verifier — +37.6% long-context DFlash decode

[HUSRCF]

Summary

Extend AlpineQ's R4/R8 Q8 multi-row verifier from #741 to exact gfx1201, based on real R9700 measurement. This changes only the Rust admission/launcher predicates and keeps the existing kernel source, arithmetic, reducer, and AlpineQ/Kaden attribution unchanged.

On the pinned 21,550-token Qwen3.8-27B XT fixture, the contributor measurement improved median DFlash decode from 23.7 to 32.6 tok/s (+37.6%).

Kaden-Schutt independently reproduced the result during maintainer review on a second R9700 (exact gfx1201, HIP 7.15). That measurement found 26.3 tok/s on the existing batched DFlash verifier and 39.3 tok/s with R4/R8 (+49.4%). The added plain-AR anchor measured 32.6 tok/s: the existing DFlash route was 19.3% slower than AR, while R4/R8 was 20.6% faster than AR.

The claim is therefore that this change repairs the long-context verifier bottleneck on the measured gfx1201 fixture, taking DFlash from a net loss to a net win over AR. It does not claim that DFlash universally outperforms AR; draft acceptance and workload remain material.

Which surface(s) does this touch?

• kernel — crates/rdna-compute
• arch crate(s): hipfire-arch-qwen35
• load
• serve
• crates/hipfire-quantize / quant formats
• control plane
• docs / CI / scripts only (the PR includes supporting env documentation and a historical checkpoint)
• policy files

The route remains fail-closed to exact gfx1100/gfx1201, Q8 KV, head dimension 128/256, sequential non-tree batches of 4..32 rows, logical context above 4096, and graph capture off. Other cases retain the established batched attention path.

Performance evidence

Hardware: Radeon AI PRO R9700, exact gfx1201, wave32, HIP 7.14.

Target SHA-256: 9f91556f7e0431a077d03756a7102d0154108757289e6e5fe9a2d204c0c9eeb7

Draft SHA-256: d0a74a232a0e2166d889f823e91e0fbf778d21dd9668d7de055cdecb065401bc

Prompt MD5: b4d0b63cddcac872648ddf3cdd92cac2 (21,550 actual tokens)

Fresh-process order was off,on,on,off,off,on; HIPFIRE_FA_PERTOKEN_MIN_CTX was the only arm delta. Both arms used Q8 VMM KV, DFlash, graph capture off, a ten-second DPM warmup, greedy sampling, and 200 output tokens.

route	samples (tok/s)	median	delta
existing batched	24.6, 23.7, 23.3	23.7	—
R4/R8 multi-row	32.6, 32.6, 32.5	32.6	+37.6%

All six runs had identical output MD5 b501ab0e0102889bd63537f2006d4f61, tau 1.80, 71 cycles, and 200 emitted tokens.

Independent maintainer re-measurement

Kaden-Schutt independently repeated the benchmark during maintainer review on a second Radeon AI PRO R9700 (exact gfx1201, HIP 7.15). The run used the same pinned target, draft and prompt; Q8 VMM KV; max_seq=65536; greedy sampling; HIPFIRE_VERIFY_GRAPH=0; one unrecorded warmup; and fresh processes for every sample. Three plain-AR anchors were added to the declared arm order.

route	samples (tok/s)	median	relative to AR
plain AR (--spec off)	32.6, 32.6, 32.6	32.6	—
DFlash, existing batched verifier	26.4, 26.3, 26.3	26.3	-19.3%
DFlash, R4/R8 multi-row verifier	39.3, 39.3, 39.3	39.3	+20.6%

R4/R8 improved DFlash throughput by 49.4% relative to the existing batched verifier. Both DFlash arms retained tau 1.80 and 71 cycles, reproducing the contributor run's draft behaviour exactly. The absolute rates differ between hosts, but the direction and mechanism reproduce independently.

This AR anchor corrects an omission in the original PR description: the existing long-context DFlash route was slower than plain AR on this fixture. The new route turns that net loss into a measured win.

The gfx1201 kernel oracle measured R4/R8 speedups of 2.08x/2.49x at context 32,768. Worst relative output error across head dimensions 128/256 and contexts through 32K was 4.765e-7 (limit 1e-3). All entries compiled with zero private scratch/spills.

Test plan

• ./scripts/no-gpu-ci.sh — local run reaches five pre-existing mq4c_repack fixture failures shared with clean beta; required CI is left to report independently
• cargo build --release clean
• cargo test --lib --workspace — claim-scoped crate suites were run instead
• hipfire-arch-qwen35: 193 passed, 4 ignored
• rdna-compute: 244 passed
• test_kernels: 16/16 on gfx1201
• test_kernelsQA --expected-arch gfx1201: 16/16
• serve_harness.py battery: 5/5 coherent; zero empty, runaway, attractor, or retrieval failures. Full JSON is posted in the evidence comment immediately below.
• LongBench-v2 hard-30, prompt_think, temperature 1.0, uncapped xhigh thinking, 64K output ceiling: 30/30 natural stops, zero runtime/output-health failures; longest output 14,940 tokens. This is quality soak evidence, not a performance A/B.
• Independent maintainer re-measurement on a second gfx1201 R9700: R4/R8 reproduced at +49.4% over the existing DFlash verifier and +20.6% over plain AR.
• Maintainer serve_harness.py --mode session validation: 8/8 turns completed normally across 7.1K–36.9K contexts, with prefix-cache hits on every continuation and zero empty, runaway or token-attractor outputs. The t7/t8 literal dedupe retrieval misses were inspected and were benign naming differences (hash_file / find_duplicates), not coherence failures.
• crate maps, env-doc scan, rustfmt, fmt-bomb, and diff checks

The multi-row route is excluded during graph capture and retained/PM4 replay, so this PR makes no Redline performance or parity claim.

Full fixture-bound measurements and ISA resources are recorded in docs/perf-checkpoints/2026-09-11-gfx1201-qwen38-multirow-verifier.md.

Hardware validation request (optional)

Manual claim-matched hardware evidence is provided above; no additional automation route is requested.

How this merges (direct review)

Merge authority remains direct maintainer review plus the required CI checks. This measurement is a promotion candidate for exact gfx1201 routing, not a registry admission or universal gfx12 claim.

Architecture-trait change?

No.

[HUSRCF]

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[Kaden-Schutt]

Independent re-measurement (maintainer review)

Reproduced the long-context A/B on a second R9700 (exact gfx1201, HIP 7.15) with the PR's recipe — Q8 VMM KV, max_seq=65536, DFlash with the pinned mq4v2 draft (sha256 d0a74a23…), HIPFIRE_VERIFY_GRAPH=0, greedy, 200 output tokens, one unrecorded warmup, fresh process per sample. HIPFIRE_DFLASH_WINDOW / HIPFIRE_DFLASH_CTX_CAP unset, so the draft loads at its declared W=2048 (all-layers sliding), matching the PR's implicit configuration. Prompt benchmarks/prompts/qwen38_issue693_longcode_20676.txt, md5 b4d0b63cddcac872648ddf3cdd92cac2, 21,550 tokens. Candidate is this PR merged onto current beta (5c6db516b), plus a pending review change that also excludes the route during retained/PM4 recording (inert on this path).

Order ar, off, on, on, off, off, on, ar, ar — the PR's declared order with three AR anchors (--spec off) added.

arm	decode tok/s (samples)	median	τ / cycles
AR, no draft (--spec off)	32.6, 32.6, 32.6	32.6	—
DFlash, existing batched route (HIPFIRE_FA_PERTOKEN_MIN_CTX=0)	26.4, 26.3, 26.3	26.3	1.80 / 71
DFlash, R4/R8 multi-row route (=4096, default)	39.3, 39.3, 39.3	39.3	1.80 / 71

• on vs off: +49.4% (PR: +37.6% from 23.7→32.6). Direction and draft behaviour (τ 1.80, 71 cycles) reproduce exactly; absolute rates are higher on both arms on this host.
• Disclosure the PR body omits, and a known defect we should state plainly: at 21.5K context, DFlash on the existing batched route is a 19% regression vs. plain AR (26.3 vs 32.6). The "+37.6%" baseline is slower than not speculating at all. The honest framing of this change is that it takes long-context DFlash on gfx1201 from a net loss to a +20.6% net win over AR (39.3 vs 32.6). Please update the summary and the perf-checkpoint to carry the AR anchor.

Coherence (VALIDATION.md serve route, product path): scripts/serve_harness.py --mode session on benchmarks/prompts/session_coding.json (md5 c0d470288bde3f1e54e4bba04da8f8a2), route on, max_seq=131072, registry sampling (T=1.0, xhigh, uncapped think), seed 7. 8/8 turns finished at stop, contexts 7.1K→36.9K (all above the 4096 threshold, 16-row verify batches), prefix cache hit on every turn (cached 7134/14601/21262/25898/32166/33107/36818), zero empty/runaway/attractor, decoded text read and on-task. The harness's literal-substring retrieval gate flagged dedupe absent on t7/t8 — the model named its functions hash_file/find_duplicates; not a coherence failure.

Identities: target sha256 9f91556f…eeb7; hipfire md5 80d89b280a57ecbd5eb1e32e1683e306; daemon md5 6e0e62f447f3f25e3a4a45637ff19d96.

Merge order is being decided alongside #755; this comment is measurement, not disposition.