[comgr][hotswap] Lower M32 scale16 WMMA exactly

[harsh-amd]

Scope

Lower M32 block-16 scale16 WMMA exactly through four block-32 operations with conservative overlap and continuation-liveness checks.

Review fixes

The review repair commits on this branch:

• keep scale-prefix operands in physical VGPR bank 0 while selecting matrix operands from their A/B banks;
• drain XCNT immediately before every generated VGPR-bank mode change;
• centralize the fail-closed legacy-B0 VOP3 scalar-source classifier and add positive/near-miss coverage;
• add focused displacement-aware LIT coverage for nonzero matrix banks, bank-zero scale operands, XCNT waits, immediate C, neg_hi, and A0-to-A0 idempotence.

The temporary exact encoding classifier is tracked by #3638 so it can be replaced by an installed MC/TargetParser API.

Review range and dependencies

• Historical clean fork PR for the original feature: [comgr][hotswap] Lower M32 scale16 WMMA exactly harsh-amd/llvm-project#15
• Original exact logical source commit: 3c9a16b20ea0f5a99563b33c41b7e8f64792994e
• Review repair commits: dc80021da911b5d1f4be07182c436784122e1daf and a655e97001fbaf18ab48cffe2d162d45fed0282f

The dependency audit found that this feature is not buildable on #3577 alone. It also consumes the finite-indirect-control-flow API represented by #3610, the current/final liveness API represented by #3618, and bank-aware helper changes from the larger cumulative stack. The clean-fork base currently imports that broader stack, so this upstream Files changed view remains cumulative.

Review status

Draft and not ready to merge. The branch must be reduced to a complete, explicit, buildable prerequisite chain after those dependencies settle. Do not merge the cumulative snapshot.

#3598 remains unchanged as the immutable 2,685/2,685 integration reference; that historical result is not a corpus qualification claim for this repaired head.

Validation of repaired cumulative head

• Release/assertions focused build: PASS
• HotswapMCTests: 214/214 PASS
• focused M32 bank-zero/XCNT LIT test: 1/1 PASS
• formatting and git diff --check: PASS

Full check-comgr, ASAN, baseline/candidate corpus comparison, and MI400-3 qualification were intentionally not started because the review/dependency/scope gate remains unresolved. They are required after the PR is made independently reviewable and buildable.

[paulzzy]

This duplicates a hard-coded instruction encoding in two patch passes:

• comgr-hotswap-patch-wmma-scale16.cpp
• comgr-hotswap-patch-wmma-split.cpp

Both independently recognize the same B0 instruction using 0xd0310000 and 0x00100000. That creates two semantic sources of truth and conflicts with amd/comgr/AGENT_CONVENTIONS.md, which requires instruction handling through the MC layer rather than duplicated opcode bytes.

I understand the A0 decoder may not represent this legacy B0 opcode directly, so a documented exception may be necessary. It should still be one shared helper with named ISA fields, an upstream issue/TODO explaining the MC-layer gap, and shared positive plus near-miss negative tests. Please refactor this before merging so the split and scale16 passes cannot drift apart.

[paulzzy]

The previous hard-coded decoder concern still applies, and I found two additional P1 numerical blockers in the exact current head c76267569454.

1. M32 maps Scale16 scale operands through the active SRC0/SRC1 VGPR-MSB banks (comgr-hotswap-patch-wmma-scale16.cpp around 733-742 and 1580-1583). Scale-prefix operands ignore VGPR-MSB and always address bank zero. With SRC0 bank 1, for example, this deinterleaves physical v296:v297 while the generated WMMA scale operand v40 consumes physical bank-zero v40. The same wrong physical mapping corrupts forward-dead analysis and scratch reservation. The current positive test uses only mode zero and masks the issue.

2. Generated M32 s_set_vgpr_msb transitions do not drain XCNT. Signed #3577 added s_wait_xcnt 0 before changed modes; M32 emits repeated transitions around VALU/WMMA scale permutations and save/restore operations without those waits. The WMMA hazard v_nop does not address XNACK replay under a later mapping.

The branch also does not actually descend from signed #3577 2c6a7286; it lacks the final bank-zero, XCNT, generated-operand, and reuse fixes despite declaring that dependency. Rebase requires real semantic conflict resolution, not a mechanical move.

Please rebase the clean M32 feature onto signed #3577, keep scale inputs and their liveness in bank zero, inherit/assert XCNT waits, and centralize the legacy B0 encoding exception used by scale16/split/control-flow code. Add nonzero-MSB bank-zero scale, later Scale/Scale16 liveness, immediate-C/neg_hi/refusal, split-bank scratch, and tensor-mask coexistence regressions.

Finally, the 2,685/2,685 evidence is translation/ELF/idempotence only; it does not establish M32 numerical equivalence. An executable trusted numerical comparison is still required. Current formatter and GCC/C++17 SCOPED_TRACE(StringRef) CI failures also remain.

[harsh-amd]

Review repair is now pushed at a655e97001fbaf18ab48cffe2d162d45fed0282f.

Resolved correctness findings:

• scale-prefix VGPRs now remain in physical bank 0 while matrix operands use their selected A/B banks;
• generated VGPR-bank changes now drain XCNT first;
• the legacy-B0 VOP3 scalar-source recognition is centralized and fail-closed, with positive and near-miss coverage; the missing installed MC classifier is tracked by AMDGPU: expose legacy stepping instruction classification through installed MC APIs #3638;
• focused displacement-aware LIT coverage now checks the bank-zero/XCNT behavior, immediate C, neg_hi, and idempotence.

Focused results on the repaired cumulative head:

• Release/assertions focused build: PASS
• HotswapMCTests: 214/214 PASS
• focused M32 LIT: 1/1 PASS

Qualification verdict remains INCONCLUSIVE. A clean dependency probe found that this change does not build on #3577 alone: it also consumes the #3610 finite-indirect-flow API, the #3618 current/final-liveness API, and bank-aware helper work from the broader cumulative stack. The PR therefore remains draft. Full check-comgr, ASAN, corpus, and MI400-3 qualification must restart after the branch is reduced to an explicit, independently buildable prerequisite chain.