Integrate riscv-dv

[tandr3w]

#163

Integrates riscv-dv testing framework

Added makefile target "riscv_dv" that runs the Python script. The Python script runs the run.py file provided by the framework, compiles using gcc with the linker script from riscof, runs using the riscof dut_sim, runs utoss_log_trace_to_csv which converts the logs to a CSV format, and runs a provided script to compare the CSV with the SAIL simulator reference model.

See the README for instructions on installing

[TheDeepestSpace]

we'll need to move this into the ci and dev dockerfiles

[TheDeepestSpace]

what's the difference between these two parameters? also we should probably feed thes from RISCOF_ISA_STRING

[tandr3w]

RISCV_DV_TARGET is the target machine that riscv-dv generates instructions for (can be rv32i, rv32imafdc, rv32imc, rv32imcb)

RISCV_DV_ISA is the format that is fed to the GCC when compiling it (-march) saying what instructions the compiiler is allowed to accept (I.e. it will error if there is an opcode that is outside of what you pass here). I think we can probably just default it to being the same as the target but with _zicsr_zifencei appended and it should be able to handle everything fine.

I'm not really sure how to derive the target from the UTOSS_RISCV_CONFIG since they don't support all the targets by default and tell you to add more by yourself if you want a custom configuration (might be a good idea):

If you want to have a custom setting for your processor, you can make a copy of existing target directory as the template, and modify riscv_core_setting.sv to match your processor capability. You can then run the generator with --custom_target <target_dir>:

Maybe we can make the script find the best matching available one automatically? I tried making an implementation of this in my current commit.

[TheDeepestSpace]

could you also configure this to run in ci? does not have to be scheduled yet -- just maybe a trial run

[tandr3w]

• Added it to CI
• Made new makefile
• Derived the target and ISA from riscv config variable

Note that the current script doesn't put everything possible in the compare CSV as the logger is missing some of it, so we might need to add more later. The address mismatch is also still an issue so it will fail if there is ever an AUIPC (which is pretty much always)

Also it seems like the pyflow part of the riscv-dv library is a little outdated so for the B extension it produces instructions that are no longer in the spec

[github-actions]

🔧 DE1-SoC Synthesis Report Summary Diff

• RV32I

  1. Fitter Summary

     @@ -1,4 +1,4 @@
     -Fitter Status : Successful - Sun Jul 19 20:27:50 2026
     +Fitter Status : Successful - Fri Jul 24 22:06:26 2026
      Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
      Revision Name : utoss-risc-v
      Top-level Entity Name : top

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• RV32IB

  1. Fitter Summary

     @@ -1,4 +1,4 @@
     -Fitter Status : Successful - Sun Jul 19 20:28:55 2026
     +Fitter Status : Successful - Fri Jul 24 22:06:47 2026
      Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
      Revision Name : utoss-risc-v
      Top-level Entity Name : top

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Comparing synthesis results from main branch vs. this PR