Integrate riscv-dv

.devcontainer/Dockerfile

@@ -136,4 +136,21 @@ RUN mkdir -p /tmp/sail-riscv && \
 USER dev
 RUN pip3 install riscof
 
+# install riscv-dv
+USER dev
+RUN pip3 install PyYAML bitstring Sphinx Pallets-Sphinx-Themes sphinxcontrib-log-cabinet \
+    sphinx-issues sphinx_rtd_theme rst2pdf flake8 pyvsc tabulate pandas
+ARG RISCV_DV_VERSION=b7a0b4b0b51346a3c64f159f81ea262d867c14a9
+ARG RISCV_DV_TAR_NAME=${RISCV_DV_VERSION}.tar.gz
+ARG RISCV_DV_TAR_URL=https://github.com/chipsalliance/riscv-dv/archive/${RISCV_DV_TAR_NAME}
+ARG RISCV_DV_TAR_HASH="e95d179b52f3c8dd1566b5b7bf6a5b42c570bfb17cca7f1f2c73460a0c5d0669  ${RISCV_DV_TAR_NAME}"
+RUN mkdir -p /tmp/riscv-dv && \
+    cd /tmp/riscv-dv && \
+    wget ${RISCV_DV_TAR_URL} && \
+    echo ${RISCV_DV_TAR_HASH} | sha256sum -c && \
+    tar -xzf ${RISCV_DV_TAR_NAME} && \
+    sudo mv riscv-dv-* /opt/riscv-dv && \
+    cd .. && rm -rf /tmp/riscv-dv
+ENV RISCV_DV_HOME=/opt/riscv-dv
+
 ENTRYPOINT ["/usr/bin/dumb-init", "--"]

.github/workflows/ci.yaml

@@ -162,6 +162,35 @@ jobs:
             riscof/riscof_work/style.css
           retention-days: 7
 
+  riscv_dv:
+    timeout-minutes: 30
+    needs: select_ci_image
+    # dont skip if build_ci_image is skipped
+    if: always()
+    runs-on: ubuntu-latest
+    container:
+      image: ${{ needs.select_ci_image.outputs.image-tag }}
+
+    strategy:
+      matrix: *utoss-risc-v-matrix
+
+    steps:
+      - name: Checkout code
+        uses: actions/checkout@v4
+
+      - name: Run riscv-dv
+        env:
+          RISCV_DV_DIR: /opt/riscv-dv
+        run: make riscv_dv UTOSS_RISCV_CONFIG=${{ matrix.config }}
+
+      - name: Upload riscv-dv logs
+        if: always()
+        uses: actions/upload-artifact@v4
+        with:
+          name: riscv-dv-logs-${{ matrix.config }}
+          path: utoss_riscv_dv/logs/**
+          retention-days: 7
+
   de1-soc:
     timeout-minutes: 30
     needs:

.gitignore

@@ -8,6 +8,7 @@ riscof/utoss_riscv/utoss_riscv_isa.yaml
 riscof/sail_cSim/__pycache__
 riscof/config.ini
 riscof/dut_sim
+utoss_riscv_dv/logs/
 
 envs/de1-soc/poc/poc*.mem
 envs/de1-soc/poc/poc*.mif

Dockerfile.ci

@@ -85,6 +85,22 @@ USER root
 RUN apt update && apt install -y python3 python3-pip && \
     pip3 install riscof
 
+# install riscv-dv
+RUN pip3 install PyYAML bitstring Sphinx Pallets-Sphinx-Themes sphinxcontrib-log-cabinet \
+    sphinx-issues sphinx_rtd_theme rst2pdf flake8 pyvsc tabulate pandas
+ARG RISCV_DV_VERSION=b7a0b4b0b51346a3c64f159f81ea262d867c14a9
+ARG RISCV_DV_TAR_NAME=${RISCV_DV_VERSION}.tar.gz
+ARG RISCV_DV_TAR_URL=https://github.com/chipsalliance/riscv-dv/archive/${RISCV_DV_TAR_NAME}
+ARG RISCV_DV_TAR_HASH="e95d179b52f3c8dd1566b5b7bf6a5b42c570bfb17cca7f1f2c73460a0c5d0669  ${RISCV_DV_TAR_NAME}"
+RUN mkdir -p /tmp/riscv-dv && \
+    cd /tmp/riscv-dv && \
+    wget ${RISCV_DV_TAR_URL} && \
+    echo ${RISCV_DV_TAR_HASH} | sha256sum -c && \
+    tar -xzf ${RISCV_DV_TAR_NAME} && \
+    mv riscv-dv-* /opt/riscv-dv && \
+    cd .. && rm -rf /tmp/riscv-dv
+ENV RISCV_DV_HOME=/opt/riscv-dv
+
 # install svlint
 USER dev
 ARG SVLINT_VERSION=0.9.3

Makefile

@@ -24,6 +24,8 @@ RISCOF_UTOSS_RISCV_ISA_CONFIG          := $(RISCOF_DIR)/utoss_riscv/utoss_riscv_
 
 UTOSS_RISCV_CONFIG ?= RV32I
 
+UTOSS_BOOT_ADDR ?= 32\'h0000_0000
+
 # Convert B extension to Zbb for RISC-V ISA spec
 RISCOF_ISA_STRING = $(subst B,Zbb,$(UTOSS_RISCV_CONFIG))
 
@@ -50,7 +52,8 @@ UTOSS_RISCV_RISCOF_VERILATOR_DEFINES := -DUTOSS_PIPELINE_LOGGER
 # ===========================
 
 VERILATOR_FLAGS := -Wall --binary --trace --timing -sv -cc -O3 $(UTOSS_RISCV_VERILATOR_DEFINES)
-RISCOF_VERILATOR_FLAGS := $(VERILATOR_FLAGS) $(UTOSS_RISCV_RISCOF_VERILATOR_DEFINES)
+TOP_VERILATOR_FLAGS := $(VERILATOR_FLAGS) -GBOOT_ADDR=$(UTOSS_BOOT_ADDR)
+RISCOF_VERILATOR_FLAGS := $(TOP_VERILATOR_FLAGS) $(UTOSS_RISCV_RISCOF_VERILATOR_DEFINES)
 
 # Testbench-only defines
 TB_DEFINES := -DTESTBENCH
@@ -91,7 +94,7 @@ run_top: $(OUT_DIR)/top_sim
 
 $(OUT_DIR)/top_sim: $(SRCS)
 	@mkdir -p $(BUILD_DIR)/top
-	$(VERILATOR) $(VERILATOR_FLAGS) \
+	$(VERILATOR) $(TOP_VERILATOR_FLAGS) \
 		--top-module top \
 		--Mdir $(BUILD_DIR)/top \
 		-o top_sim \
@@ -181,6 +184,8 @@ riscof_run: $(RISCOF_UTOSS_RISCV_ISA_CONFIG) $(RISCOF_CONFIG) riscof_build_dut
 		--suite=riscv-arch-test/riscv-test-suite/ \
 		--env=riscv-arch-test/riscv-test-suite/env
 
+include utoss_riscv_dv/Makefile
+
 # sidekick image builds
 GITHUB_CONTAINER_REGISTRY=ghcr.io
 GITHUB_ORG_NAME=utoss
@@ -207,4 +212,5 @@ svlint_tb:
 .PHONY: all build_top run_top build_tb run_tb new_tb \
         svlint svlint_tb \
         riscof_build_dut riscof_validateyaml riscof_clone_archtest \
-        riscof_generate_testlist riscof_run FORCE
+        riscof_generate_testlist riscof_run \
+        riscv_dv FORCE

envs/simulation/memory.sv

@@ -3,7 +3,9 @@
 
 // a dual-read single-write memory block that we use with our core in simulation environment
 module memory
-  #( parameter SIZE = 1024 )
+  #( parameter SIZE = 1024
+  , parameter addr_t BOOT_ADDR = addr_t'(0)
+  )
   ( input wire clk
 
   , mem_bus.memory i_bus
@@ -32,16 +34,25 @@ module memory
     end
   end
 
-  wire unused = &{d_bus.address[`PROCESSOR_BITNESS -1:SIZE_W], d_bus.address[1:0], i_bus.address[`PROCESSOR_BITNESS -1:SIZE_W], i_bus.address[1:0]};
+  addr_t d_base_address;
+  addr_t i_base_address;
+
+  assign d_base_address = d_bus.address - BOOT_ADDR;
+  assign i_base_address = i_bus.address - BOOT_ADDR;
+
+  wire unused = &{d_base_address[`PROCESSOR_BITNESS -1:SIZE_W]
+                , d_base_address[1:0]
+                , i_base_address[`PROCESSOR_BITNESS -1:SIZE_W]
+                , i_base_address[1:0]};
 
   always @(posedge clk) begin
-    d_bus.read_data <= M[d_bus.address[SIZE_W + 1:2]];
-    i_bus.read_data <= M[i_bus.address[SIZE_W + 1:2]];
+    d_bus.read_data <= M[d_base_address[SIZE_W + 1:2]];
+    i_bus.read_data <= M[i_base_address[SIZE_W + 1:2]];
 
-    if (d_bus.write_enable[0]) M[d_bus.address[SIZE_W +1:2]][7:0] <= d_bus.write_data[7:0];
-    if (d_bus.write_enable[1]) M[d_bus.address[SIZE_W +1:2]][15:8] <= d_bus.write_data[15:8];
-    if (d_bus.write_enable[2]) M[d_bus.address[SIZE_W +1:2]][23:16] <= d_bus.write_data[23:16];
-    if (d_bus.write_enable[3]) M[d_bus.address[SIZE_W +1:2]][31:24] <= d_bus.write_data[31:24];
+    if (d_bus.write_enable[0]) M[d_base_address[SIZE_W +1:2]][7:0] <= d_bus.write_data[7:0];
+    if (d_bus.write_enable[1]) M[d_base_address[SIZE_W +1:2]][15:8] <= d_bus.write_data[15:8];
+    if (d_bus.write_enable[2]) M[d_base_address[SIZE_W +1:2]][23:16] <= d_bus.write_data[23:16];
+    if (d_bus.write_enable[3]) M[d_base_address[SIZE_W +1:2]][31:24] <= d_bus.write_data[31:24];
   end
 
 endmodule

envs/simulation/top.sv

@@ -2,7 +2,9 @@
 `include "src/interfaces/mem_bus.svh"
 
 module top
-  #( parameter MEM_SIZE = 1024 ) //maybe change to 2048 if using dual port?
+  #( parameter MEM_SIZE = 1024 //maybe change to 2048 if using dual port?
+  , parameter addr_t BOOT_ADDR = addr_t'(0)
+  )
   ( input wire clk
   , input wire reset
   );
@@ -11,15 +13,20 @@ module top
   mem_bus d_bus();
 
   wire unused = &{i_bus.write_data, i_bus.write_enable};
-  memory #( .SIZE ( MEM_SIZE ) )
+  memory
+    #( .SIZE      ( MEM_SIZE      )
+    , .BOOT_ADDR ( BOOT_ADDR     )
+    )
     u_memory
       ( .clk   ( clk )
 
       , .d_bus ( d_bus.memory )
       , .i_bus ( i_bus.memory )
       );
 
-  utoss_riscv core
+  utoss_riscv
+    #( .BOOT_ADDR ( BOOT_ADDR ) )
+    core
     ( .clk   ( clk   )
     , .reset ( reset )
 

riscof/dut.sv

@@ -2,12 +2,16 @@
 
 `include "test/utils.svh"
 
-module dut;
+module dut
+  #( parameter logic [31:0] BOOT_ADDR = 32'h0000_0000 );
 
   reg clk;
   reg reset;
 
-  top #( .MEM_SIZE ( 500000 /* 2MB */ ) )
+  top
+    #( .MEM_SIZE      ( 500000 /* 2MB */ )
+     , .BOOT_ADDR     ( BOOT_ADDR        )
+     )
     top
       ( .clk   ( clk   )
       , .reset ( reset )
@@ -33,7 +37,7 @@ module dut;
 
   task watch_tohost();
     /* verilator lint_off UNUSEDSIGNAL */
-    integer tohost;
+    integer tohost, tohost_local;
     reg [31:0] tohost_data;
     /* verilator lint_on UNUSEDSIGNAL */
 
@@ -43,7 +47,8 @@ module dut;
 
       while (tohost_data === 0 || tohost_data === 32'bx) begin
         @(posedge clk);
-        tohost_data = top.u_memory.M[19'(tohost[31:2])];
+        tohost_local = tohost - BOOT_ADDR;
+        tohost_data = top.u_memory.M[19'(tohost_local[31:2])];
       end
 
       $display("%m: memory[tohost] written <%0d> at time %t", tohost_data, $time);
@@ -68,7 +73,7 @@ module dut;
     /* verilator lint_off UNUSEDSIGNAL */
     integer begin_signature, end_signature;
     string sig_filename;
-    integer sig_file, i;
+    integer sig_file, i, i_local;
     //integer i_fixed;
     /* verilator lint_on UNUSEDSIGNAL */
 
@@ -90,7 +95,8 @@ module dut;
     sig_file = $fopen(sig_filename, "w");
     if (sig_file != 0) begin
       for (i = begin_signature; i < end_signature; i = i + 4) begin
-        $fwrite(sig_file, "%08x\n", top.u_memory.M[19'(i[31:2])]);
+        i_local = i - BOOT_ADDR;
+        $fwrite(sig_file, "%08x\n", top.u_memory.M[19'(i_local[31:2])]);
       end
       $fclose(sig_file);
       $display("%m: signature written to %s", sig_filename);

src/modules/Logger.sv

@@ -225,7 +225,8 @@ module Logger
                             );
 
                         $display
-                            ( "MEM: addr=%08h we=%b wdata=%08h rdata=%08h alu_result=%08h rd=%s result_src=%0d regwrite=%0b"
+                            ( "MEM: pc=%08h addr=%08h we=%b wdata=%08h rdata=%08h alu_result=%08h rd=%s result_src=%0d regwrite=%0b"
+                            , mem_stage.pc_cur
                             , dmem_address
                             , dmem_write_enable
                             , dmem_write_data
@@ -237,7 +238,8 @@ module Logger
                             );
 
                         $display
-                            ( "WB : rd=%s(%0d) regwrite=%0b result_src=%0d wb_result=%08h alu_result=%08h"
+                            ( "WB : pc=%08h rd=%s(%0d) regwrite=%0b result_src=%0d wb_result=%08h alu_result=%08h"
+                            , wb_stage.pc_cur
                             , reg_name(wb_rd)
                             , wb_rd
                             , wb_stage.reg_write

src/stages/fetch_stage.sv

@@ -5,6 +5,7 @@
 `include "src/interfaces/ex_to_if_if.svh"
 
 module fetch_stage
+  #( parameter addr_t BOOT_ADDR = addr_t'(0) )
   ( output if_to_id_t if_to_id
   , input ex_to_if_t  ex_to_if
 
@@ -51,10 +52,10 @@ module fetch_stage
     endcase
 
   always_ff @ (posedge clk)
-    if (!stall_f) pc_cur <= reset ? 0 : pc_next;
+    if (!stall_f) pc_cur <= reset ? BOOT_ADDR : pc_next;
 
   always_ff @ (posedge clk)
-    if (!stall_f) pc_prev <= reset ? 0 : pc_cur;
+    if (!stall_f) pc_prev <= reset ? BOOT_ADDR : pc_cur;
 
   // With synchronous instruction memory, one in-flight instruction can arrive after stall_f rises.
   // Keep a one-entry skid copy so decode can consume it once the stall is released;

src/utoss_riscv.sv

@@ -9,6 +9,7 @@
 
 // pipelined implementation of our core
 module utoss_riscv
+  #( parameter addr_t BOOT_ADDR = addr_t'(0) )
   ( input wire       clk
   , input wire       reset
   , mem_bus.consumer i_bus
@@ -37,7 +38,9 @@ module utoss_riscv
 
   // fetch stage start (@thatlittlegit)
 
-  fetch_stage u_fetch_stage
+  fetch_stage
+    #( .BOOT_ADDR ( BOOT_ADDR ) )
+    u_fetch_stage
     ( .if_to_id ( if_to_id_out )
     , .ex_to_if ( ex_to_if_out )
 

utoss_riscv_dv/Makefile

@@ -0,0 +1,31 @@
+RISCV_DV_DIR         ?= $(if $(RISCV_DV_HOME),$(RISCV_DV_HOME),$(HOME)/tools/riscv-dv)
+RISCV_DV_OUT         ?= utoss_riscv_dv/logs/out_utoss_smoke
+RISCV_DV_TEST        ?= utoss_rv32i_basic_smoke
+RISCV_DV_TESTLIST    ?= utoss_riscv_dv/utoss_riscv_dv_smoke.yaml
+RISCV_DV_SIMULATOR   ?= pyflow
+RISCV_DV_MABI        ?= ilp32
+RISCV_DV_ISS         ?= sail
+RISCV_DV_SEED        ?=
+RISCV_DV_GEN_TIMEOUT ?= 3600
+RISCV_DV_ARGS        ?=
+
+RISCV_DV_TARGET ?= $(shell printf '%s' '$(UTOSS_RISCV_CONFIG)' | tr '[:upper:]' '[:lower:]')
+
+# Note: The provided IMCB target uses outdated instructions so will not work
+RISCV_DV_ISA ?= $(shell printf '%s' '$(subst B,_Zba_Zbb_Zbc_Zbs,$(UTOSS_RISCV_CONFIG))_zicsr_zifencei' | tr '[:upper:]' '[:lower:]')
+
+riscv_dv:
+	python3 utoss_riscv_dv/utoss_riscv_dv.py \
+		--repo-root . \
+		--riscv-dv-dir $(RISCV_DV_DIR) \
+		--output $(RISCV_DV_OUT) \
+		--test $(RISCV_DV_TEST) \
+		--testlist $(RISCV_DV_TESTLIST) \
+		--simulator $(RISCV_DV_SIMULATOR) \
+		--target $(RISCV_DV_TARGET) \
+		--isa $(RISCV_DV_ISA) \
+		--mabi $(RISCV_DV_MABI) \
+		--iss $(RISCV_DV_ISS) \
+		$(if $(RISCV_DV_SEED),--seed $(RISCV_DV_SEED)) \
+		$(if $(RISCV_DV_GEN_TIMEOUT),--gen-timeout $(RISCV_DV_GEN_TIMEOUT)) \
+		$(RISCV_DV_ARGS)

utoss_riscv_dv/README.md

@@ -0,0 +1,24 @@
+To install riscv-dv:
+
+```
+sudo apt update
+sudo apt install -y git python3 python3-pip make
+
+mkdir -p ~/tools
+git clone https://github.com/chipsalliance/riscv-dv.git ~/tools/riscv-dv
+cd ~/tools/riscv-dv
+
+pip3 install -r requirements.txt
+pip3 install --user -e .
+
+echo 'export PATH=$HOME/.local/bin:$PATH' >> ~/.bashrc
+echo 'export RISCV_DV_HOME=$HOME/tools/riscv-dv' >> ~/.bashrc
+source ~/.bashrc
+```
+
+Usage:
+```
+make riscv_dv
+```
+
+TODO: Delete this README and add to wiki?