feat: STM32 Add option for UART to use DMA for sending byte

build-internals/build.zig

@@ -275,6 +275,8 @@ pub const Stack = union(enum) {
     address: usize,
     /// Place the stack at the end of the n-th ram memory region.
     ram_region_index: usize,
+    /// Place the stack at the end of the named ram memory region.
+    ram_region_name: []const u8,
     /// Place the stack at a symbol's address.
     symbol_name: []const u8,
 };

build.zig

@@ -340,6 +340,17 @@ pub fn MicroBuild(port_select: PortSelect) type {
                         }
                     } else @panic("no ram memory region found for setting the end-of-stack address");
                 },
+                .ram_region_name => |name| blk: {
+                    for (target.chip.memory_regions) |region| {
+                        if (region.name) |region_name| {
+                            if (std.mem.eql(u8, region_name, name)) {
+                                if (region.tag == .ram) {
+                                    break :blk .{ .address = region.offset + region.length };
+                                } else @panic("Named region found is not a ram region");
+                            }
+                        }
+                    } else @panic("no ram memory named region found for setting the end-of-stack address");
+                },
                 .symbol_name => |name| .{ .symbol_name = name },
             };
 

core/src/cpus/cortex_m.zig

@@ -789,7 +789,7 @@ pub const startup_logic = struct {
         @compileError("`_vector_table` is not available in a RAM image. Use `ram_vector_table` instead.");
     } else if (using_ram_vector_table)
         .{
-            .initial_stack_pointer = microzig.config.end_of_stack,
+            .initial_stack_pointer = microzig.config.end_of_stack.address orelse @panic("EndOfStack is not define"),
             .Reset = .{ .c = microzig.cpu.startup_logic._start },
         }
     else
@@ -1003,7 +1003,7 @@ pub const debug = struct {
 };
 
 const is_ram_image = microzig.config.ram_image;
-const using_ram_vector_table = @hasField(CPU_Options, "ram_vector_table") and microzig.options.cpu.ram_vector_table;
+pub const using_ram_vector_table = @hasField(CPU_Options, "ram_vector_table") and microzig.options.cpu.ram_vector_table;
 
 pub fn export_startup_logic() void {
     if (is_ram_image) {

examples/stmicro/stm32/build.zig

@@ -24,7 +24,8 @@ pub fn build(b: *std.Build) void {
         .{ .target = stm32.boards.stm32f3discovery, .name = "STM32F303_HTS221", .file = "src/hts221.zig" },
         .{ .target = stm32.boards.stm32l476discovery, .name = "STM32L476Discovery_Lcd", .file = "src/stm32l476/lcd.zig" },
         .{ .target = stm32.boards.stm32l476discovery, .name = "STM32L476Discovery_Blinky", .file = "src/blinky.zig" },
-        .{ .target = stm32.boards.stm32l476discovery, .name = "STM32L476Discovery_HTS211", .file = "src/hts221.zig" },
+        .{ .target = stm32.boards.stm32l476discovery, .name = "STM32L476Discovery_HTS221", .file = "src/hts221.zig" },
+
         .{ .target = stm32.chips.STM32F103C8, .name = "STM32F1xx_blink", .file = "src/blinky.zig" },
         .{ .target = stm32.chips.STM32F100RB, .name = "STM32F1xx_semihost", .file = "src/semihosting.zig" }, //QEMU target: stm32vldiscovery
         .{ .target = stm32.chips.STM32F103C8, .name = "STM32F1xx_adc", .file = "src/stm32f1xx/adc.zig" },

examples/stmicro/stm32/src/hts221.zig

@@ -7,12 +7,13 @@ const HTS221 = microzig.drivers.sensor.HTS221;
 
 pub const microzig_options: microzig.Options = .{
     .logFn = microzig.board.uart_logger.log,
-    .interrupts = .{
-        .SysTick = .{ .c = systick.SysTick_handler },
+    .cpu = .{
+        .ram_vector_table = true,
     },
 };
 
 pub fn init() void {
+    stm32.dma.DMA1_Channel4.enable_interrupt();
     board.init();
     board.init_log();
     systick.init() catch {
@@ -21,6 +22,7 @@ pub fn init() void {
 }
 
 pub fn main() !void {
+    std.log.info("Starting main", .{});
     const clock = try stm32.systick_timer.clock_device();
     var i2c1 = board.i2c1();
     try i2c1.apply();

examples/stmicro/stm32/src/stm32f1xx/adc_dualmode.zig

@@ -11,7 +11,7 @@ const dma = stm32.dma;
 const AdvancedADC = stm32.adc.AdvancedADC;
 const time = stm32.time;
 
-const adc_dma = dma.Channel.init(.DMA1, 0);
+const adc_dma = dma.DMA1_Channel1;
 const uart = stm32.uart.UART.init(.USART1);
 
 const TX = gpio.Pin.from_port(.A, 9);
@@ -48,8 +48,9 @@ pub fn main() !void {
     const adc1 = AdvancedADC.init(.ADC1);
     const adc2 = AdvancedADC.init(.ADC2);
     var adc_buf: [2]AdcData = undefined;
+    const dma_channel = adc_dma.get_channel();
 
-    adc_dma.apply(.{
+    dma_channel.apply(.{
         .circular_mode = true,
         .memory_increment = true,
 
@@ -62,7 +63,7 @@ pub fn main() !void {
         .periph_address = @intFromPtr(&adc1.regs.DR),
         .mem_address = @intFromPtr(&adc_buf),
     });
-    adc_dma.start();
+    dma_channel.start();
 
     TX.set_output_mode(.alternate_function_push_pull, .max_50MHz);
     ADC_pin1.set_input_mode(.analog);

examples/stmicro/stm32/src/stm32f1xx/advanced_adc.zig

@@ -19,7 +19,7 @@ const dma = stm32.dma;
 const AdvancedADC = stm32.adc.AdvancedADC;
 const time = stm32.time;
 
-const adc_dma = dma.Channel.init(.DMA1, 0);
+const adc_dma = dma.DMA1_Channel1;
 const uart = stm32.uart.UART.init(.USART1);
 const adc = AdvancedADC.init(.ADC1);
 
@@ -66,8 +66,9 @@ pub fn main() !void {
 
     const ref_ovf_flag: *volatile bool = &ovf_flag;
     var adc_buf: [10]u16 = .{0} ** 10;
+    const dma_channel = adc_dma.get_channel();
 
-    adc_dma.apply(.{
+    dma_channel.apply(.{
         .circular_mode = true,
         .memory_increment = true,
 
@@ -80,7 +81,7 @@ pub fn main() !void {
         .periph_address = @intFromPtr(&adc.regs.DR),
         .mem_address = @intFromPtr(&adc_buf),
     });
-    adc_dma.start();
+    dma_channel.start();
 
     //configure UART log
 

port/stmicro/stm32/build.zig

@@ -44,6 +44,7 @@ pub fn init(dep: *std.Build.Dependency) Self {
                 .hal = microzig.HardwareAbstractionLayer{
                     .root_source_file = b.path("src/hals/STM32F303.zig"),
                 },
+                .stack = .{ .ram_region_name = "CCMRAM" },
             }),
             .stm32f4discovery = chips.STM32F407VG.derive(.{
                 .board = .{

port/stmicro/stm32/build.zig.zon

@@ -19,5 +19,6 @@
         "build.zig",
         "build.zig.zon",
         "src",
+        "ld",
     },
 }

port/stmicro/stm32/ld/dma_sram.ld

@@ -0,0 +1,14 @@
+/**
+ * Adding a buffer for DMA. This buffer need to be in 
+ * specific region so that the BuxMatrix can connect DMA and specific RAM
+ * We assume that the generated linker have a ram named SRAM connected to DMA
+ * Check the list of ram region inside the src/Chip.zig file for your target.
+ */
+
+ SECTIONS {
+    .dma_buffer (NOLOAD) :
+    {
+        KEEP(*(.dma_buffer))
+    } > SRAM
+ }
+ INSERT BEFORE .heap;