[Seq] Update HWMemSimImpl's replSeqMem to support higher latency. #9383
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Historically, we have only replaced FIRRTL memories with readLatency and writeLatency of 1 with external modules for macro replacement. The latency is an intrinsic behavior of the memory, but doesn't affect its interface when we are doing external module replacement. Since some users are trying to enable higher latency memory models, and replace them with external modules that either model this in simulation or with a macro for synthesis. This lifts the restriction, allowing such higher latency memories to also be replaced by external modules similar to memories with latency of 1.
seldridge
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seldridge
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LGTM
Please work with @tmckay-sifive to figure out how to define what these latencies actually mean, how they interact with different clocks, and get it into the FIRRTL spec. The real question here is I think around the conflict behavior for different read/write latencies. E.g., if the read and write latencies are both 10, then when do you have a conflict? For the full duration? At some point in the middle?
We should then make sure that for the non-repl-seq-mem path, that the in-tree memory model matches this.
Semi-related: fixing this in the background would be good: #787
One actual review question: are these latencies recorded in the resulting repl-seq-mem JSON format?
| // CHECK-NOT: infer_mux_override | ||
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| // COM: Check repl-seq-mem for readLatency = 0, writeLatency = 1 | ||
| // REPL-SEQ-MEM-NOT: hw.module.extern @FIRRTLMem_1_1_1_16_1_0_1_0_0 |
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Possibly just REPL-SEQ-MEM-NOT: hw.module.extern.
Historically, we have only replaced FIRRTL memories with readLatency and writeLatency of 1 with external modules for macro replacement. The latency is an intrinsic behavior of the memory, but doesn't affect its interface when we are doing external module replacement.
Since some users are trying to enable higher latency memory models, and replace them with external modules that either model this in simulation or with a macro for synthesis. This lifts the restriction, allowing such higher latency memories to also be replaced by external modules similar to memories with latency of 1.