TLVDS

TLVDS_IBUF

This device is supported in Apicula

Ports

Port	Size	Direction
I	1	input
IB	1	input
O	1	output

Verilog Instantiation

TLVDS_IBUF tlvds_ibuf_inst (
    .I(I),
    .IB(IB),
    .O(O)
);

TLVDS_IBUF_ADC

The Gowin TLVDS_IBUF_ADC primitive is a true LVDS (Low Voltage Differential Signaling) input buffer used in conjunction with an ADC (Analog-to-Digital Converter) module. It is designed to implement ADC dynamic voltage source selection, with inputs for differential signals A and B, as well as a dynamic enable signal. The primitive takes these inputs and provides a output that can be used by the ADC module.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
ADCEN	1	input
I	1	input
IB	1	input

Verilog Instantiation

TLVDS_IBUF_ADC tlvds_ibuf_adc_inst (
    .ADCEN(ADCEN),
    .I(I),
    .IB(IB)
);

TLVDS_IOBUF

This device is supported in Apicula

Ports

Port	Size	Direction
I	1	input
IO	1	inout
IOB	1	inout
O	1	output
OEN	1	input

Verilog Instantiation

TLVDS_IOBUF tlvds_iobuf_inst (
    .I(I),
    .IO(IO),
    .IOB(IOB),
    .O(O),
    .OEN(OEN)
);

TLVDS_OBUF

This device is supported in Apicula.

Ports

Port	Size	Direction
I	1	input
O	1	output
OB	1	output

Verilog Instantiation

TLVDS_OBUF tlvds_obuf_inst (
    .I(I),
    .O(O),
    .OB(OB)
);

TLVDS_OEN_BK

This device is not yet supported in Apicula

Ports

Port	Size	Direction
OEN	1	input

Parameters

Parameter	Default Value
OEN_BANK	0

Verilog Instantiation

TLVDS_OEN_BK #(
    .OEN_BANK(OEN_BANK)
) tlvds_oen_bk_inst (
    .OEN(OEN)
);

TLVDS_TBUF

This device is supported in Apicula.

Ports

Port	Size	Direction
I	1	input
O	1	output
OB	1	output
OEN	1	input

Verilog Instantiation

TLVDS_TBUF tlvds_tbuf_inst (
    .I(I),
    .O(O),
    .OB(OB),
    .OEN(OEN)
);