Yosys ‐ synth_gowin

The synth_gowin command in Yosys performs synthesis for Gowin FPGA devices. This command transforms RTL into a netlist that can be used with the subsequent tools in the open source Gowin toolchain.

Basic Usage

yosys -p "read_verilog input.v; synth_gowin -json output.json"

Important Options

Output Format Options

• -json <file> - Generate JSON netlist compatible with nextpnr-himbaechel for the open source flow (recommended)
• -vout <file> - Generate Verilog netlist output that can be imported into the proprietary Gowin IDE

Top Module Specification

• -top <module> - Specify the top-level module (default is 'top')

Optimization Options

• -retime - Enable register retiming optimization using ABC with -dff -D 1 options
• -noflatten - Preserve design hierarchy by disabling flattening
• -nowidelut - Avoid using muxes to implement LUTs larger than LUT4s

Memory and Storage Options

• -nobram - Disable use of block RAM cells (forces use of distributed RAM)
• -nolutram - Disable use of distributed RAM cells (forces use of block RAM)
• -no-rw-check - Disables checking for read/write collisions in memory. Only use if you are certain your design handles memory access conflicts correctly, as this can lead to broken designs with undefined behavior.

Architecture-Specific Options

• -nodffe - Avoid using flip-flops with clock enable
• -noalu - Disable use of arithmetic logic units
• -noiopads - Skip adding IO buffers to top-level ports
• -noabc9 - Disable the new ABC9 optimization flow

Common Use Cases

Basic RTL to JSON

yosys -p "read_verilog design.v; synth_gowin -json design.json"

Multiple Input Files with Custom Top Module

yosys -p "read_verilog mod1.v mod2.v mod3.v; synth_gowin -top my_top -json output.json"

Optimization for Timing

yosys -p "read_verilog design.v; synth_gowin -retime -json design.json"

Memory Implementation Control

Gowin FPGAs support two types of memory implementation:

1. Block RAM (BRAM): Dedicated memory blocks built into the FPGA fabric

   • Efficient for larger memories
   • Limited resource, fixed locations
   • Best for larger, synchronous memories

   yosys -p "read_verilog design.v; synth_gowin -nolutram -json design.json"

2. Distributed RAM: Implemented using the FPGA's LUTs

   • More flexible placement
   • Uses general-purpose logic resources
   • Better for small, fast memories

   yosys -p "read_verilog design.v; synth_gowin -nobram -json design.json"

Choose the implementation based on your design's size, speed, and resource requirements.

Troubleshooting with -no* Options

The various -no* options can be used to disable advanced features when troubleshooting synthesis issues:

1. Timing Issues

   • Try -nodffe to eliminate clock enable logic
   • Use -noalu to avoid complex arithmetic structures

2. Resource Usage Problems

   • Use -nobram or -nolutram to control RAM implementation
   • Try -nowidelut if experiencing LUT-related issues

3. Optimization Issues

   • Try -noabc9 to use simpler optimization algorithms

Integration with Tool Flow

The synth_gowin command generates a JSON netlist that serves as input for the next step in the toolchain.

For details on the subsequent steps:

• Place and Route: See nextpnr-himbaechel documentation
• Bitstream Generation: See gowin_pack documentation

Tips and Best Practices

1. Always start with the basic options before adding optimizations
2. Use -retime when timing is critical
3. Consider memory implementation carefully based on your design's needs
4. When debugging, disable features one at a time using -no* options to isolate issues
5. Keep top-level module names consistent across your project
6. Verify synthesis results with the built-in stat command